8255 Programmable Peripheral Interface Register usage 19880619/WJ van Ganswijk 0 rw port a 1 rw port b r bbbbbbbb read port w bbbbbbbb write port 2 rw port c r bbbbbbbb read port w 0...nnn0 set bit nnn (0..7) w 0...nnn1 reset bit nnn (0..7) w 1...bbbb set 4 least bits according to bbbb w .xxx.... don't care for port c the use of the bits is as follows: m0 m1 m2 cntl rw xxxxxxxx - general i/o bits w rw 1....... a output buffer full r rw .1...... a interrupt enable1 rw r xx...... - general i/o bits r rw ..1..... a input buffer full r rw ...1.... a interrupt enable2 rw w ..xx.... - general i/o bits rw rw rw ....1... a interrupt rw .....1.. b interrupt enable w ......1. b output buffer full r ......1. b input buffer full rw .......1 b interrupt rw .....xxx - general i/o bits 3 w control .......1 port c (b0..b3) is input/output ......1. port b is input/output .....1.. group b mode 1/0 ....1... port c (b4..b7) is input/output ...1.... port a is input/output .00..... group a mode 0 .01..... group a mode 1 .x1..... group a mode 2 1....... mode set flag active *end