//scc68070.h
//define the io-registers of the scc68070
//19910720/wjvg, to c

//!!!this include file doesn't like compilers that align long's!!!

//latched interrupt descriptor
#define lid_p   (*(unsigned char *)0x80001000)  //priority

//iic controller
#define iic_d   (*(unsigned char *)0x80002001)  //data
#define iic_a   (*(unsigned char *)0x80002003)  //address
#define iic_s   (*(unsigned char *)0x80002005)  //status
#define iic_c   (*(unsigned char *)0x80002007)  //control
#define iic_cl  (*(unsigned char *)0x80002009)  //clock

//uart, subset of 2641, 2661, 2691
#define uart_m  (*(unsigned char *)0x80002011)  //mode
#define uart_s  (*(unsigned char *)0x80002013)  //status
#define uart_cl (*(unsigned char *)0x80002015)  //clock
#define uart_c  (*(unsigned char *)0x80002017)  //command
#define uart_t  (*(unsigned char *)0x80002019)  //transmit
#define uart_r  (*(unsigned char *)0x8000201b)  //receive

//timer
#define timer_s  (*(unsigned char  *)0x80002020)  //status
#define timer_c  (*(unsigned char  *)0x80002021)  //control
#define timer_r  (*(unsigned short *)0x80002022)  //reload
#define timer_Av ( (unsigned short[])0x80002024)  //array of timer values
#define timer_v0 (*(unsigned short *)0x80002024)  //value 0
#define timer_v1 (*(unsigned short *)0x80002026)  //value 1
#define timer_v2 (*(unsigned short *)0x80002028)  //value 2

//peripheral interrupt controller
#define pic_c1   (*(unsigned char  *)0x80002045)  //control 1
#define pic_c2   (*(unsigned char  *)0x80002047)  //control 2

//dma controllers, compatible with 68430,68440,68450
#define Adma ((struct sdma[2])0x80004000)  //array of descriptors

//the registers per dma controller
struct sdma {
  unsigned char  dma_s;             //status
  unsigned char  dma_e;             //error
  unsigned short dma_0;             //reserved
  unsigned char  dma_dc;            //device control
  unsigned char  dma_oc;            //operation control
  unsigned char  dma_sc;            //sequence control
  unsigned char  dma_cc;            //channel control
  unsigned short dma_1;             //reserved
  unsigned short dma_mtc;           //memory transfer counter
  unsigned long  dma_mac;           //memory address counter
  unsigned long  dma_2;             //reserved
  unsigned long  dma_dac;           //device address counter
  unsigned char  dma_3[0x2d-0x10];  //reserved
  unsigned char  dma_cp;            //channel priority
  unsigned char  dma_4[0x40-0x2e];  //reserved
};

//memory management unit
//downward compatible with 68910 and 68920 (in contiguous segment mode)
#define mmu_s (*(unsigned char *)0x80008000)  //status
#define mmu_c (*(unsigned char *)0x80008001)  //control

#define Aseg ((struct sseg[8])0x80008040)  //array of descriptors

//descriptor per segment
struct sseg {
  unsigned short seg_c;  //control
  unsigned short seg_l;  //length
  unsigned char  seg_0;  //reserved
  unsigned char  seg_n;  //segmentnumber
  unsigned short seg_a;  //address
};

//segment descriptor attributes
#define AT_ST  0x0040        //stack segment
#define AT_W   0x0800        //write permission
#define AT_R   0x1000        //read permission
#define AT_X   0x2000        //execute permission
#define AT_S   0x4000        //supervisor mode verplicht
#define AT_RW  (AT_R |AT_W)  //alleen lezen en schrijven
#define AT_RX  (AT_R |AT_X)  //alleen lezen en uitvoeren
#define AT_RWX (AT_RW|AT_X)  //alles toegestaan

#define MMU_EN 0x80  //enable mmu

//exception record on the stack
struct sexcep {
  unsigned short ex_sr;
  unsigned long  ex_pc;      //watch-out for alignment!
  unsigned short ex_forvek;
  unsigned short ex_ssw;
  unsigned short ex_mm;
  unsigned long  ex_itn0;
  unsigned long  ex_tpd;
  unsigned long  ex_tpf;
  unsigned long  ex_dbin;
  unsigned short ex_ir;
  unsigned short ex_irc;
  unsigned short ex_itn1;
};

//interrupt levels
#define LV_TIMER 1  //timer
#define LV_UARTT 2  //uart transmitter
#define LV_UARTR 3  //uart receiver
#define LV_I2C   4  //uart i2c-bus controller

//end