//am29xxx.h //definitions for the 29xxx-familie //19930603/wjvg //global registers #define REG_GR 0x00 // 0, global registers #define REG_IP 0x00 // 0, indirect pointer register #define REG_RSP 0x01 // 1, stack pointer #define REG_ACC 0x60 // 96, accumulator //#define REG_MFP 0x78 //120, memory frame pointer (wjvg), nee lokaal #define REG_TAV 0x79 //121, trap handler argument #define REG_TPC 0x7a //122, trap handler return address #define REG_LRP 0x7b //123, large return pointer #define REG_SLP 0x7c //124, static link pointer #define REG_MSP 0x7d //125, memory stack pointer #define REG_RAB 0x7e //126, register allocate bound #define REG_RFB 0x7f //127, register free bound //local registers #define REG_LR 0x80 //128, local registers #define REG_LR0 0x80 //128, local register 0, return address #define REG_LR1 0x81 //129, local register 1, frame pointer //protected special purpose registers #define REG_SR 0x00 // 0, special registers #define REG_VAB 0x00 // 0, vector area base address #define REG_OPS 0x01 // 1, old processor status #define REG_CPS 0x02 // 2, current processor status #define REG_CFG 0x03 // 3, configuration #define REG_CHA 0x04 // 4, channel address #define REG_CHD 0x05 // 5, channel data #define REG_CHC 0x06 // 6, channel control #define REG_RBP 0x07 // 7, register bank protect #define REG_TMC 0x08 // 8, timer counter #define REG_TMR 0x09 // 9, timer reload #define REG_PC0 0x0a //10, program counter 0 #define REG_PC1 0x0b //11, program counter 1 #define REG_PC2 0x0c //12, program counter 2 #define REG_MMU 0x0d //13, memory management unit, (-29200) #define REG_LRU 0x0e //14, least recently used entry, (-29200) //de speciale user-registers #define REG_IPC 0x80 //128, indirect pointer c #define REG_IPA 0x81 //129, indirect pointer a #define REG_IPB 0x82 //130, indirect pointer b #define REG_Q 0x83 //131, register q #define REG_ALU 0x84 //132, ALU status #define REG_BP 0x85 //133, byte pointer #define REG_FC 0x86 //134, funnel-shift count #define REG_CR 0x87 //135, count remaining //virtual special purpose registers #define REG_FPE 0xa0 //160, floating point environment (virtual) #define REG_INTE 0xa1 //161, integer environment (virtual) #define REG_FPS 0xa2 //162, floating point status (virtual) //old processor status (ops), 16-7 //current processor status (cps), 16-1 #define CPS_DA (1<< 0) //disable all interrupts and traps #define CPS_DI (1<< 1) //disable interrupts #define CPS_IM0 (0<< 2) //interrupt mask==0, intr(0..0) enabled #define CPS_IM1 (1<< 2) //interrupt mask==1, intr(0..1) enabled #define CPS_IM2 (2<< 2) //interrupt mask==2, intr(0..2) enabled #define CPS_IM3 (3<< 2) //interrupt mask==3, intr(0..3)+internal ints enabled #define CPS_F_IM (1<< 2) //faktor for interrupt mask #define CPS_M_IM (3<< 2) //masker for interrupt mask #define CPS_SM (1<< 4) //supervisor mode #define CPS_PI (1<< 5) //physical addressing instructions (-29200) #define CPS_PD (1<< 6) //physical addressing data (-29200) #define CPS_WM (1<< 7) //wait mode #define CPS_RE (1<< 8) //ROM enable (-29200) #define CPS_LK (1<< 9) //lock (-29200) #define CPS_FZ (1<<10) //freeze #define CPS_TU (1<<11) //trap unaligned access #define CPS_TP (1<<12) //trace pending #define CPS_TE (1<<13) //trace enable #define CPS_IP (1<<14) //interrupt pending #define CPS_CA (1<<15) //coprocessor active (-29200) #define CPS_MM (1<<16) //monitor mode? (29050) #define CPS_TD (1<<17) //timer (interrupt) disable (29200) //configuration (cfg), 2-28 #define CFG_CD ( 1<< 0) //branch target cache disable (-29200) #define CFG_CP ( 1<< 1) //coprocessor present (-29200) #define CFG_BO ( 1<< 2) //byte order (-29200) #define CFG_RV ( 1<< 3) //ROM vector area (-29200) #define CFG_VF ( 1<< 4) //vector fetch (-29200) #define CFG_F_PRL ( 1<<24) //faktor for processor release level #define CFG_M_PRL (0xff<<24) //masker for processor release level //channel control (chc), 16-19 #define CHC_CV ( 1<< 0) //contents valid #define CHC_NN ( 1<< 1) //not needed #define CHC_F_TR ( 1<< 2) //factor for target register #define CHC_M_TR (0xff<< 2) //masker for target register #define CHC_ST ( 1<<13) //set #define CHC_ML ( 1<<14) //multiple operation #define CHC_LS ( 1<<15) //load/store #define CHC_F_CR ( 1<<16) //factor for load/store count remaining (-1) #define CHC_M_CR (0xff<<16) //masker for load/store count remaining (-1) #define CHC_F_CNTL ( 1<<24) //faktor for kopie van CNTL veld uit instruktie #define CHC_M_CNTL (0x7f<<24) //masker for kopie van CNTL veld uit instruktie //timer reload (tmr), 16-23 #define TMR_IE (1<<24) //interrupt enable #define TMR_IN (1<<25) //interrupt #define TMR_OV (1<<26) //overflow //alu status (alu), 2-16 #define ALU_F_FC ( 1<< 0) //faktor for funnel shift count #define ALU_M_FC (31<< 0) //masker for funnel shift count #define ALU_F_BP ( 1<< 5) //faktor for byte pointer #define ALU_M_BP ( 3<< 5) //masker for byte pointer #define ALU_C ( 1<< 7) //carry #define ALU_Z ( 1<< 8) //zero #define ALU_N ( 1<< 9) //negative #define ALU_V ( 1<<10) //overflow #define ALU_DF ( 1<<11) //divide flag //floating point environment (fpe), 2-15 #define FPE_NM (1<< 0) //invalid operation mask #define FPE_RM (1<< 1) //reserved operation mask #define FPE_VM (1<< 2) //overflow mask #define FPE_UM (1<< 3) //underflow mask #define FPE_XM (1<< 4) //inexact result mask #define FPE_DM (1<< 5) //divide by zero mask #define FPE_F_FRM (1<< 6) //faktor for floating-point round mode #define FPE_M_FRM (3<< 6) //masker for floating-point round mode #define FPE_FF (1<< 8) //fast float select //integer environment (inte), 2-16 #define INTE_MO (1<< 0) //integer multiplication overflow exception mask #define INTE_DO (1<< 1) //integer division overflow exception mask //floating point status (fps), 2-19 #define FPS_NS (1<< 0) //invalid operation sticky #define FPS_RS (1<< 1) //reserved operation sticky #define FPS_VS (1<< 2) //overflow sticky #define FPS_US (1<< 3) //underflow sticky #define FPS_XS (1<< 4) //inexact result sticky #define FPS_DS (1<< 5) //divide by zero sticky #define FPS_NT (1<< 8) //invalid operation trap #define FPS_RT (1<< 9) //reserved operand trap #define FPS_VT (1<<10) //overflow trap #define FPS_UT (1<<11) //underflow trap #define FPS_XT (1<<12) //inexact result trap #define FPS_DT (1<<13) //divide by zero trap //de interruptnummers #define INT_OPCODE 0x00 // 0, illegal opcode #define INT_ALIGNMENT 0x01 // 1, alignment error #define INT_OVERFLOW 0x02 // 2, overflow or underflow #define INT_PROTECTION 0x05 // 5, protection violation #define INT_UIMM 0x08 // 8, user instruction mapping miss #define INT_UDMM 0x09 // 9, user data mapping miss #define INT_SIMM 0x0a //10, supervisor instruction mapping miss #define INT_SDMM 0x0b //11, supervisor data mapping miss #define INT_TIMER 0x0e //14, timer interrupt #define INT_TRACE 0x0f //15, trace interrupt #define INT_INTR0 0x10 //16, intr0 interrupt #define INT_INTR1 0x11 //17, intr1 interrupt #define INT_INTR2 0x12 //18, intr2 interrupt #define INT_INTR3 0x13 //19, intr3 interrupt #define INT_TRAP0 0x14 //20, trap0 interrupt #define INT_TRAP1 0x15 //21, trap1 interrupt #define INT_FP_EXCEP 0x16 //22, floating point exception #define INT_OPCODE_D8 0x18 //24, opcode 0xd8.. #define INT_MULTM 0x1e //30, multm instruction #define INT_MULTMU 0x1f //31, multmu instruction #define INT_MULTIPLY 0x20 //32, multiply instruction #define INT_DIVIDE 0x21 //33, divide instruction #define INT_MULTIPLU 0x22 //34, multiplu instruction #define INT_DIVIDU 0x23 //35, dividu instruction #define INT_CONVERT 0x24 //36, convert instruction #define INT_SQRT 0x25 //37, sqrt instruction #define INT_CLASS 0x26 //38, class instruction #define INT_OPCODE_E7 0x27 //39, opcode 0xe7 #define INT_OPCODE_E8 0x28 //39, opcode 0xe8 #define INT_OPCODE_E9 0x29 //39, opcode 0xe9 #define INT_FEQ 0x2a //42, feq instruction #define INT_DEQ 0x2b //43, deq instruction #define INT_FGT 0x2c //44, fgt instruction #define INT_DGT 0x2d //45, dgt instruction #define INT_FGE 0x2e //46, fge instruction #define INT_DGE 0x2f //47, dge instruction #define INT_FADD 0x30 //48, fadd instruction #define INT_DADD 0x31 //49, dadd instruction #define INT_FSUB 0x32 //50, fsub instruction #define INT_DSUB 0x33 //51, dsub instruction #define INT_FMUL 0x34 //52, fmul instruction #define INT_DMUL 0x35 //53, dmul instruction #define INT_FDIV 0x36 //54, fdiv instruction #define INT_DDIV 0x37 //55, ddiv instruction #define INT_OPCODE_F8 0x38 //56, opcode 0xf8 #define INT_OPCODE_F9 0x39 //57, opcode 0xf9 #define INT_OPCODE_FA 0x3a //58, opcode 0xfa #define INT_OPCODE_FB 0x3b //59, opcode 0xfb #define INT_OPCODE_FC 0x3c //60, opcode 0xfc #define INT_OPCODE_FD 0x3d //61, opcode 0xfd #define INT_OPCODE_FE 0x3e //62, opcode 0xfe #define INT_OPCODE_FF 0x3f //63, opcode 0xff #define V_SPILL 0x40 //spill registers #define V_FILL 0x41 //fill registers //end