74303 8-line inverting/noninverting divide by 2 clock driver. Six outputs in phase with CLK, two out of phase. +----------+ Q3 |1 +--+ 16| Q2 Q4 |2 15| Q1 GND |3 14| /RST GND |4 74 13| VCC GND |5 303 12| VCC Q5 |6 11| CLK Q6 |7 10| /PRE /Q7 |8 9| /Q8 +----------+ [This information is part of the GIICM]