Ah, what the heck: Here is the uncorrected scan, as a puzzle: MPU Interface As illustrated in the functional block diagram, the ADV476 sup- Ports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM . The RSO and RSI control inputs specify whether the MPU is accessing the address register or the color palette RAM, as shown in Table I. The 8-bit address register is used to address the color palette RAM, eliminating the requirement for external address multiplexers. RSI RSO AddressedbyMPU 0 O Pixel Address Register (RAM Write Mode) I 1 Pixel Address Register (RAM Read Mode) 0 1 Color Palette RAM 1 O Pixel Read Mask Register Table I. Control Input Truth Table To write color data, the MPU writes to the address register with the S-bit address of the color palette RAM location which is to be modified. The MPU performs three successive write cycles (six bits of red data, sLu bits of green data and siu bits of blue data). During the blue write cycle, the three bytes of color in- formation are concatenated into an is-bit word and written to the location specified by the address register. The address regis- ter then automatically increments to the next location which the MPU may modify by simply writing another sequence of red, green and blue data. To read back color data, the MPU loads the address register with the address of the color palette RAM location to be read. The MPU performs three successive read cycles (6 bits each of red, green and blue data). Following the blue read cycle, the address register increments to the next location which the MPU may read by simply reading another sequence of red, green ant blue data. This 6bit color data is right justified, i.e., the lower six bits of the data bus with DO being the LSB and DS the MSB. D6 and D7 are ignored during a color write cycle and are set to zero during a color read cycle. During color palette RAM access, the address register resets to OOH following a blue read or write operation to RAM location FFH. The MPU interface operates asynchronously to the pixel clock. Data transfers between the color palette RAM and the color ree isters (R, G, and B in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. Color (RGB) data is normally loaded to the color palette RAM during video screen retrace, i.e., during the video waveform blanking period, see Figure 5. To keep track of the red, green and blue readlwrite cycles, t~e address register has two additional bits (ADDRa, ADDRb) thal count module three, as shown in Table II. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other eight bits of the address register, incremented following a blue read or write cycle, (ADDR~7) are accessible to the MPU, and are used ta address color palette RAM locations, as shown in Table III. ADDRO is the LSB when the MPU is accessing the RAM. The MPU may read the address register at any time without modify ing its contents or the existing read/write mode. Figure 1 illustrates the MPU read/write timing and Table III shows the associated functional instructions. Value 1 RS1 I RSO I Addressed by MPU ADDRa,b (Counts Module 3) 1 00 1 I ) Red Value 01 1 I I Green Value 10 1 I I Blue Value ADDRO-7 (Counts Binary) I OOH-FFH I 0 I 1 I Color Palette RAM Table N. Address Register ~ADDRJ Operation Value RSI RSO AddressedbyMPU ADDRa,b (Counts Module 3j 00 Red \'alue 01 GreenValue 10 Blue Value ADDRO-7 (Counts Binary) OOH-FFH O Color Palette RAM Table Il. Address Register IADDRI Operation RD WR RSO RSI ADDRa ADDRbJOperationPerlormed 1 0 0 O X X I WrileAddressRegister; DO-D7-tADDR~7 0 -, ADDRa,b 1 0 1 0 0 0 ( Write Red Value; Increment ADDRa-b 1 0 1 0 0 1 Write Green Value; Inciement ADDRa-b 1 0 1 0 1 0 I Write Blue Value; Modify RAM Location inclement ADDRO-7 Inc~ement ADDRa-b 0 1 1 1 X X Read Address Register; AD;bRO-7 -,DO-D7 0 1 1 0 0 O Read Red Value; Increment ADDRa-b 0 1 1 0 0 1 I Read Green Value; Increment ADDRa-b 0 1 1 0 1 0 I Read Blue Value; Inerkment ADDRO-7 Incrkment ADDRa-b 0 O X X X X I Invalid Operation Table 111. Truth Table for Read/Write Operations ;ITAL-TO-ANALOG CONVERTERS rrallre oulleT mrerrace The PO-P7 inputs are used to address the color palate RAM, a sho~vn in Table IV. These inputs are latched on the rising edge of PICLK and address any of the 256 locations in thecolor pal- erre RAM. The addressed location contains 18 bits D F color (6 bits of red, 6 bits of green and 6 bits of blue) information. This data i, transferred to the three DACs and is then cnnverted to an analog output (RED, GREEN, BLUE), these out puts then control the red, green and blue electron guns in themoniror. The BLANK input is also latched on the rising edge of PCLK. This is to maintain synchronization with the color da ra. P~P7 I Addressed by Frame Buffer 0011 ) Color I-'aicrre RAM Location OOH 01H I Color Palette RAM Location 01H FFH ) ColorPaletreKAM Location FFH Table IV. Pixel Select/Color Palette Control Tru!h Table Piuel Read Mask Register The Pixel Read Mask Register in the ADV476 can be used to implement register level pixel processing, thereby ca;ing down on software overhead. This is achieved by gating theinput pixel Strealn (FO-P7) with the contents of the pixel read mask regis ICr. The operation is a bitwise logical ANDing of the pixel data. l`ht· Fonrents of this register can be accessed and altered at any "me by the MPU (DO-D7). Table I shows the rele~anr control ilpnals. This pixel masking operation can be used to alter the displayed colors without changing the contents of either the video frame buffer or the color palette RAM. The effect of this operation is to partition the color palette into a user determined number of color planes. This process can be used for special effects includ- ing animation, overlays and flashing objects. Success, Jaap