Chip Directory
Mirror sites
Mailing list
Forum
Have this site translated
 Embedded Systems
Host site

Addressing example

Here is an email answering some practical addressing questions.

From Jaap van Ganswijk <ganswijk@xs4all.nl>
To Hantzley Tauckoor
Subject Re: Seeking for assistance

At 19980912 Hantzley Tauckoor wrote:

I am a student of Computer Science and Engineering at the university of Mauritius and I am working on a mini project on the "Computer System Organisation of The 8080A and The 8085". I am facing some difficulties particularly when memory is concerned.
I would be very grateful if you could help me in my work. It would be a great asset for me to have the advice of a professional.
I am to devise a memory map for a partcular microprocessor system which has 16 address lines and 8 data lines in the system bus. My major problem is that I'll have to use 1 chip for the ROM( 4 KB ) and 3 chips For the RAM*( equal size each ). I really have no idea how to tackle this problem.
First I'd like to show my idea and later you tell me if its wrong or not. If the system has 16 address lines, then I would get 64 KB for the addresses in the total memory. Now if I substract 4 KB for the ROM, I would have 60 KB for the RAM* and this is to be divided into 3 chips of equal size. So finally I will get 20 KB for each RAM* chips- which I find difficult, if not impossible, to implement. Moreover, I have the constraint that all logic implementations should be done using only NAND* gates or DECODERS.

Having 20 Kbyte SRAM*'s is very unusual. If you really need to use three chips (why not one?) then it's best to use 16 Kbyte chips.

Please consider that the 8080 and 8085 have their vectors in the start of the memory, so that's where the code needs to be, so there is where you will want to put your ROM.

The memory map will become:

0000 ROM
4000 RAM0
8000 RAM1
c000 RAM2

To select the chips, you'll need to decode a15 and a14:

a15 a14 device
0 0 ROM
0 1 RAM0
1 0 RAM1
1 1 RAM2

It's easy to transform this table to formulas and devise a schematics consisting of NAND*'s only... Assuming that the RAMs have an inverted select pin:

For example for RAM1:

But it's much easier to use halve a 74ls139. You just connect a14 and a15 to the selection inputs and use the 4 outputs.

Please note that the ROM will be 4 times in the memory map this way, since a13 and a12 aren't used.

Perhaps you could send me documents on that issue or the title of
any reference book where I could get the solution for this problem, or
you could share with me your ideas for this problem.

It's probably also explained in 'The art of electronics book'. See ../chipdir/ext/book/tutorial.htm

Moreover, If a total of 16 I/O ports are available, how can these be accessed.

Using the in and out instructions...

The 8080 and 8085 have 256 ports, I am quite sure...
Only use a0..a3 and your 16 ports will be 16 times in the I/O space....


Ad for PCI video capturing boards by Dektec.
Goto: Main Mirror About Author
Register: Yourself Company
Feedback: Correction Addition Question Forum
Request quote: Chips (Deutsch) Chips (English) Chips (Nederlands)

Advertisement by Adprov

Viewable with any browser


Site version is  Version GIF
Page last edited on 20030709
Page was never integrally checked for link correctness